Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. For example, metrology processes are used to measure one or more characteristics of a wafer such as dimension (e.g., line width, thickness, etc.) of features formed on the wafer during a process step, wherein the quality of the process step can be determined by measuring the one or more characteristics. One such characteristic includes overlay error. An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). The structures may take the form of gratings, and these gratings may be periodic. If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. Overlay error is the misalignment between any of the patterns used at different stages of semiconductor integrated circuit manufacturing. Conventionally, understanding of the variation across die and wafer are limited to the fixed sampling and hence overlay error is detected only for the known selected sites.
FIG. 1 illustrates a typical overlay target of the prior art. FIG. 1 illustrates an overlay target having 180 degree and 90 degree rotational symmetry, respectively, about a center of symmetry. The target structures 102, 106 of FIG. 1 include pattern elements 104, 108, which are positioned periodically with a fixed pitch between pattern elements 104, 108 within each target structure 102, 106.
Moreover, if a measured characteristic, such as overlay error, of the wafer is unacceptable (e.g., out of a predetermined range for the characteristic), the measurement of the one or more characteristics may be used to alter one or more parameters of the process such that additional wafers manufactured by the process have acceptable characteristics.
In the case of overlay error, an overlay measurement may be used to correct a lithography process in order to keep overlay errors within desired limits. For example, overlay measurements may be fed into an analysis routine that calculates “correctables” and other statistics, which may be used by the operator in order to better align the lithography tool used in the wafer processing.
The measurement of overlay error between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. Presently, overlay measurements are performed via test patterns that are printed together with layers of the wafer. The images of these test patterns are captured via an imaging tool and an analysis algorithm is used to calculate the relative displacement of the patterns from the captured images. Such overlay metrology targets (or ‘marks’) generally comprise features formed in two layers, the features configured to enable measurement of spatial displacement between features of the layers (i.e., the overlay or displacement between layers).
There are, however, a number of disadvantages to using metrology processes and tools to measure one or more characteristics of a wafer for process monitoring and control applications. For example, contemporary semiconductor devices include elements having different center-to-center distances (pitch). An overlay calibrated to align elements having a certain pitch may be ineffective to align elements having a different pitch. Using metrology measurements acquired with an overlay calibrated for a certain pitch may not provide sufficient information about the characteristic(s) of the wafers such that the process can be accurately monitored and controlled.
Consequently, it may be desirable to provide a method and system which provide alignment information useful for a variety of device pitches, allowing for more accurate measurements of a selected wafer to provide adequate correctable information.